This invention relates generally to the field of computer memory circuits and more particularly relates to a method to protect against the loss of computer operations after manufacture and sale of the computer resulting from failure of a register/arrays associated with only one thread of operation.
As consumers of computer processing services, businesses dread the occurrence of down time resulting from a computer failure, yet these events actually happen in any number of ways. A hard drive with data that hasn""t been backed-up may crash and the data may be lost. A larger fear, perhaps, is when the processor core of a computer fails to perform properly. New or additional memory will not render the computer functional: the computer itself is broke! Such loss of processing power can be disastrous to many businesses; recall a particular airline""s dilemma when its routing and scheduling was unavailable for many hours. Millions and even up to billions of dollars can be lost resulting from downtime of computers.
To avoid the failure of a computer after its components have been fabricated and assembled and the computer has been sold, many manufacturers test their processors and memory components before the computers are sold to customers and eliminate the computer components having errors. In spite of the best efforts to detect and eliminate defective computer processors, computer hardware may still fail during normal stressed processing operations at a customer""s location. One type of failure of a processor may be attributed, inter alia, to AC defects of the general and special purpose registers within the processor core and of the computer""s main random access memory caused by stressing the components under normal usage.
Some tests are performed at the customer""s location, e.g., static random access memory (SRAM) arrays are typically tested at boot-up. If a processor fails its test, it is marked as a xe2x80x9cfailurexe2x80x9d and the system is typically disabled until customer service appears. In the case of multiple processors, a particular processor may be disabled leaving the other processors to take on extra processing so that computer performance is compromised until customer services arrives.
SRAMs, however, do not have multithreaded memory cells. Currently, if a failure occurs in a multithreaded memory array or register, the multithreaded computer system displays an error code indicating a failure as data collision from multiple threads and either the entire system is disabled or, if the system is made up of multiple processors, it operates without the failing processor. In any event, the processor having the failed thread is disabled and processing is compromised.
There is a need in the industry of multithreaded computers to detect defects in registers and/or memory arrays having multithreaded storage cells during normal processing operations. If only those storage elements in a multithreaded memory or register associated with a failed thread becomes unavailable to the processor, the processor itself would not have to be disabled; rather the processor could continue normal processing of the other thread(s) which don""t have defective storage elements and could reroute the thread associated with the defective storage elements to intact storage elements. This method would still keep the processor in service rather than disabling the entire processor.
These needs and others that will become apparent to one skilled in the art are satisfied by a method to continue normal computer processing in a hardware multithreaded computer processing system executing a plurality of threads despite the failure of one of the threads, the method comprising the steps of: executing instructions of at least one of the threads in a hardware multithreaded processor having a plurality of hardware register/arrays, each one of the register/arrays associated with each one of the threads; performing a test on a particular thread and the at least one register/array associated with the particular thread; detecting the failure of the at least one register/array associated with the particular thread; disabling the failed register/array associated with the particular thread; and rerouting data of the particular thread to other individual register/arrays that are not defective.
The register/array may be a multithreaded register/array having multithreaded storage cells each comprising a number of storage elements each associated with one thread. In this case, the method of the invention to continue normal computer processing in a hardware multithreaded computer processing system executing a plurality of threads despite the failure of one of the threads comprises the steps of: executing instructions of at least one of the plurality of threads in a hardware multithreaded processor having at least one multithreaded register/array with individual storage elements associated with each of the plurality of threads; performing a test on a particular thread and the at least one multithreaded register/array having individual storage elements associated with the particular thread; detecting the failure of at least one individual storage element associated with the particular thread; disabling all storage elements associated with the particular thread; and rerouting data of the particular thread to other individual storage elements associated with other of the plurality of threads not having defective storage elements.
The method may further comprise generating an error signal indicating failure of the at least one individual storage element associated with the particular thread. Normal processing of the other threads not having defective storage elements may continue.
The step of performing a test on a particular thread and the at least one multithreaded register/array having individual storage elements associated with the particular thread may further comprise running a functional test to execute instructions under stressed processing conditions. Alternatively, the test may be a n ABIST and/or LBIST test.
The step of disabling all storage elements associated with the particular thread may comprise generating a thread select signal to select others of individual storage elements associated with other threads. In another embodiment, the step of disabling all storage elements associated with the particular thread further may comprise disabling all or some of a plurality of thread switch control events pertaining to the particular thread in a thread switch control register.
The invention may further be considered a multithreaded computer system capable of disabling one thread in the field comprising: at least one multithreaded computer processor; at least one thread switch control register for each of a plurality of threads of operation in the multithreaded computer processor; at least one hardware multithreaded memory/register array having multithreaded storage cells in which each of the storage cells has a storage element uniquely associated with one thread; a main memory connected to the at least one multithreaded computer processor; a bus interface connecting the multithreaded computer processor and the main memory to at least one of the group consisting of: a plurality of data storage devices, one or more external communication networks, one or more input/output devices for providing user input to/from the computer processor; a functional test generator to perform a functional test of at least one thread in the multithreaded computer processor in the field during normal processing; a storage element failure detector which detects the failure of a storage element uniquely associated with the thread undergoing the functional test; a storage element disabler to disable all the storage elements associated with the thread experiencing the failure in the functional test; a data rerouter to redirect data from the thread to storage elements associated with other threads to continue processing; and an error signal generator to propagate a message indicating that the one thread has failed.
The invention is also a program product for use with a hardware multithreaded computer processor for detecting the failure of one of a plurality of threads of operation, the program product comprising a signal-bearing medium carrying thereon: a functional test having a series of instructions of at least one of the plurality of threads; a thread disabler to disable individual storage elements in multithreaded storage cells in hardware registers/memory arrays; the disabled individual storage elements each associated with the at least one thread failing the functional test; a data rerouter to reconfigure any programmable registers to reroute data of the at least one thread failing the functional test to other storage elements in multithreaded storage cells associated with other threads not failing the functional test; and an error message generator to indicate that the at least one thread failed the functional test.